1. Field of Invention
The present invention relates to the methods and means for yield enhancement of stacked or three dimension integrated circuits.
2. State of the Art
Two Dimensional [2D] Integrated Circuits [ICs] are in general designed without the capability for Yield Enhancement as an active circuit means incorporated into the design or operation of 2D integrated circuitry. The primary means for achieving Yield Enhancement or economically acceptable yields of 2D circuits is semiconductor process technology. There are well know exceptions, however, such as DRAM or FLASH memory circuits and FPGA [Field Programmable Gate Arrays] circuits, and in these circuits in addition to the use of process technology, Yield Enhancement is implemented through first performing functional testing the 2D IC and then by manual or external intervention means disabling defective portions of the 2D IC. The defective circuit portions are always replaced with a spare or redundant circuit portion identical to the defective portion, and such defective circuit portions are eliminated from use with the 2D IC, wherein the loss of use of the defective portions does not change the operational capacity of the 2D IC which is a preset specification value.
The present primary means that enables the yield of present 2D ICs is the manufacturing processes used in the fabrication of the 2D IC. Semiconductor manufacturing process technology attempts to maximize the yield or number of defect free 2D ICs on a semiconductor wafer. The wafer is the basic unit of measure for semiconductor IC manufacturing process yield, semiconductor process yield is calculated by dividing the number of accepted and or defect free 2D ICs by the total number of 2D ICs on the wafer.
The Yield Enhancement circuitry used in today's 2D ICs is in general referred to as reconfiguration circuitry. This reconfiguration circuitry when it exists is used only during the testing of the IC as part of the manufacturing process, and may consist of fuse or anti-fuse circuitry that permanently changes the interconnect structure of the IC such that it is able to function in a defect free manner consistent with its design specification. Reconfiguration of these ICs may also be achieved by use of a laser to cut interconnections for the purpose of isolating a defective circuit portion. In all cases, however, the reconfiguration of these ICs is accomplished by first performing functional testing of the IC as a whole, wherein all circuit portions of the IC with the exception of any spare circuit portions are executed or brought into operation and only through said full functional testing are defects found. It is important to note for the purposes of this discussion, that current IC testing means do not test 2D ICs by specific testing of a circuit portions of an IC which is or can be isolated from other portions of the IC during testing. The CVI circuit configuration method for yield enhancement is predominately a large grain circuitry configuration herein examples of large grain circuitry are a bus channel or sub-channel with several thousands of transistors or a circuit portion or ALU circuitry of tens of thousands of transistors or more. Present 2D reconfiguration methods use a fine grain circuit element with examples such as a redundant memory column and spare FPGA gates, wherein this reconfiguration circuitry have typically sizes of 1,000 transistors or less.
Test of a 2D IC is done by functional test of the circuit as a whole. The testing of a 2D IC is performed by external test equipment and this testing determines the presence of the then existing circuit defects and whether or not these defects can be corrected by the use of small grain reconfiguration of the circuit under test or the substitution of the defective circuitry with the available spare circuitry. Once the reconfiguration process is implemented, the 2D IC is again tested. This method of test and reconfiguration of the 2D IC is a static process and only done in conjunction with external test equipment and only done as part of the manufacturing process of the IC and typically is not and or cannot be repeated once the IC is installed for its intended application in an electronic assembly.
Methods of fabrication of 3D ICs and apparatus for said methods are disclosed in U.S. Pat. Nos. 5,354,695, 5,915,167 and 7,402,897 of the present inventor and are herein incorporated by reference.